ALCCS    -    NEW SCHEME

Code: CT12                                                                 Subject: COMPUTER ARCHITECTURE

Time: 3 Hours                                                                                                     Max. Marks: 100

NOTE:

· Question 1 is compulsory and carries 28 marks. Answer any FOUR questions from the rest.  Marks are indicated against each question.

· Parts of a question should be answered at the same place.

Q.1      a. Write a brief note on Instruction Pipelining in RISC computer

b. Convert 0.859375 to Binary equivalent

             c.  What do you understand by PC relative addressing? Give an application of this mode of addressing.

             d.  Explain briefly write-through or store-through method in the context of cache memory.  

             e.  Draw a daisy chaining scheme to assign order of priority of interrupts. Indicate briefly the arbitration method.

             f. What do you understand by the terms “loosely coupled” and “tightly coupled” in parallel computers?

             g. Describe in brief Four page replacement policies.                                                   (74)

Q.2      a. A job consists of 4 tasks, taking 20 ns, 10 ns, 15 ns and 20 ns to execute. Use pipelining

and show the speed up and efficiency for 120 jobs.     

             b.  Give the steps for generation of hamming code for transmission of six bit information.          

     c.  Design a sequence detector to detect ‘111’ in data stream.                                      (5+5+8)

Q.3     a.  Give the flow chart and data flow of multiplication for multiplying (124)₁₀ with (256)₁₀

by using booth’s  algorithm.                                                                                          

             b.  Give the trace of RTL code for the BCD shift-add algorithm.                                         (10+8)

   Q.4   a.   Microprocessor instruction set includes the following instructions. Classify each                          instruction as data movement, data operation or program control.                           

(i) XTOY (x = y)

(ii)  CLRX (x = 0)

(iii)  JXT (if x = 1, then go to T)                                                                                   

                        (iv)  XMLY (x = x*y)                                                                                                  

                        (v)   XNEG (x = + 1)

             b.  What is flag register? How it is used in controlling the execution flow of the program?          

c.  Discuss different types addressing nodes with an example. Why do we have various types of addressing?                                                                                                                                 (5+5+8)

Q.5          Design a CPU that meets the following specifications:

· It can access 64 words of memory. Each word being 8 bit wide.

· It can execute the following instruction set

Instruction	Instruction Code	Operation
SUB	00 AAAAAA	AC AC-M[AAAAAA] -1
OR	01 AAAAAA	AC AC VM[AAAAAA]
ADD	10 AAAAAA	AC AC+M[AAAAAA]
JMP	11 AAAAAA	PC PC+00AAAAAA

                  Assume any other data that you may require.                                                               (18)

Q.6     a.  Explain the concept of memory segmentation used in memory management.                    

             b. Explain various page replacement policies with reference to the memory management.

             c.  Suppose a SRAM has an access time of 5 ns. DRAM with an access time of 60 ns

                  and disk space with an access time 7 msec. If the hit rate at each level in the

                  memory hierarchy is 80 % (except the last), what is the average memory

                  access time? What is the average memory access time if the hit rate at each

                  level except the last is 90%.                                                                                  (6+6+6)

Q.7     a.  Explain how processes are synchronized in shared memory computers.

b.  Explain the difference between superscalar & very large instruction word (VLIW) architecture in terms of hardware and software requirement.                              (8+10)